Clock recovery circuits are used in interfaces for interconnecting logic ICs and boards in many fields such as personal computers, work stations, network devices, computer peripherals, consumer devices and the like.
Examples of configurations of conventional clock recovery circuits, include one which employs a phase-locked loop (referred to as a “PLL” below), one which receives multiphase clock signals to select among multiphase clock signals a signal of which phase is locked to that of a received data signal, and one which uses a gated voltage-controlled oscillator (referred to as a “gated VCO” below).
A clock recovery circuit that uses a PLL comprises a phase comparator, a charge pump, a loop filter and a voltage-controlled oscillator (VCO). The phase comparator compares a phase of a received data signal and a phase of a clock signal which is output from the VCO and fed back to the comparator and the oscillation frequency of the VCO is adjusted by the phase comparator and charge pump so that a phase of the received data signal and a phase of a clock signal output from the VCO are synchronized. As a result, a clock signal locked to the received data signal is recovered. With this technique, the oscillation frequency of the VCO may be the full rate of n [Hz] or the half-rate of n/2 [Hz] with respect to a received data signal having a speed of n [bps].
A clock recovery circuit that selects from multiphase clock signals a clock signal of which a phase is locked to that of a received data signal comprises a multiphase clock generating circuit, a phase comparator, a counter and a selector. The multiphase clock generating circuit generates a plurality of clock signals which have different phases, as well as a frequency that is the full rate of n [Hz] or the half-rate of n/2 [Hz], with respect to a received data signal having a communication speed of n [bps]. The phase comparator compares the phases of a regenerated clock and received data signal and outputs, to the counter, information as to whether the regenerated clock signal leads or lags behind the received data signal. The counter outputs a phase selection signal, which is for advancing or retarding the phase of the regenerated clock signal, depending upon the information from the phase comparator. The selector, which receives the multiphase clock signals output from the multiphase clock generating circuit and the phase selection signal output from the counter, selects a clock signal locked to the received data signal from clock signals output from the multiphase clock generating circuit, and outputs the selected clock signal.
A technique employing the gated VCO is equipped with a VCO that can be switched between an oscillating state and a quiescent state by a gating signal. A clock signal locked to the received data signal is regenerated by controlling the oscillation and quiescence of the VCO in conformity with a change in the received data signal that is supplied to the VCO. This method is advantageous in that a clock signal locked to the received data signal can be recovered by a simple circuit.
By way of example, see the specification of Japanese Patent Kokai Publication JP-A-6-53950 (paragraphs 0022 to 0035 and FIG. 4) and the specification of Japanese Patent Kokai Publication JP-A-8-213979 (paragraphs 0023 to 0029 and FIGS. 1, 2).